1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to capacitor design and cell isolation methods used to reduce the surface area occupied by a DRAM cell. More specifically, the present invention forms a DRAM capacitor under the access transistor thus increasing DRAM cell density by at least about two fold over currently fabricated DRAM cells. 2. Background Art
Various DRAM capacitor designs have been employed to reduce the surface area occupied by a single DRAM cell. Early DRAM designs employed flat horizontal capacitor plates. Later designs, intended to conserve chip surface area, employed trenches or fin structures to form narrow dimension capacitors with some vertical contribution to the capacitor plate surface area.
In addition to the shape and size of the capacitor plates, the type of cell isolation contributes to the overall DRAM cell size. Traditionally, field oxide produced by the Local Oxidation of Silicon process (LOCOS) was used as cell isolation. Unfortunately, a field oxide must cover a fairly wide area in order to effectively isolate adjacent cells. Further, it is difficult to control the growth of field oxide. Therefore, field oxide often occupies a significant amount of the chip surface area.
More recently, trench isolation has been employed. This involves etching a narrow isolation trench around the active areas (cells) on the chip. The isolation trenches are then filled with oxide or other dielectric to effectively isolate adjacent active areas from one another. While trench isolation requires more process steps than LOCOS, trench isolation can be made much narrower than LOCOS oxide. Therefore, DRAMs employing trench isolation can be packed more densely than DRAMs employing field oxide (LOCOS) isolation.
In the continuing quest for higher density DRAMs, improved structures that conserve wafer surface are still needed.
The present invention addresses this need by providing a DRAM cell where an electrically insulating support structure serves as a scaffolding for capacitor formation and also electrically isolates adjacent DRAM cells. Integration of capacitor formation with DRAM cell isolation increases DRAM cell density by at least about two fold over currently fabricated DRAM cells.
In one aspect, the instant invention provides a DRAM cell comprised of a pass (or access) transistor, an electrically isolating support structure and a capacitor electrically coupled with the pass transistor that is formed on the vertical sidewalls of the support structure. The support structure isolates the DRAM cell from one or more adjacent DRAM cells. The capacitor is comprised of a first capacitor plate, a dielectric layer and a second capacitor plate. The first capacitor plate is defined by first conductive layer at the sidewall of the support structure. The second capacitor plate is defined by a second conductive layer adjacent to the support structure. The first and second capacitor plates are separated by the dielectric layer.
The pass transistor is a MOS device that may have a drain electrically connected to the first capacitor plate and electrically isolated from the second capacitor plate. In one embodiment, the support structure is between about 0.1 micrometer and about 10 micrometers. In a preferred embodiment, the support structure includes at least one of oxide (e.g., a spin on glass), nitride, or other low dielectric constant material. In one specific embodiment, the support structure includes oxide.
In one embodiment, the first conductive layer includes at least one of n-doped polysilicon and p-doped polysilicon. In another embodiment, the first conductive layer is between about 200 angstroms and about 1000 angstroms thick. In one embodiment the second conductive layer includes at least one of n-doped epitaxial silicon and p-doped epitaxial silicon. In another embodiment, the second conductive layer is between about 0.2 micrometers and about 7 micrometer high.
The dielectric layer may be made from any suitable material that can be formed in the necessary size and shape. Suitable dielectric materials include at least one of SiO2, Si3Nx, silicon oxynitride, ONO (SiO2/Si3Nx/SiO2) layered material), tantalum pentaoxide (Ta2O5), barium strontium titanate BaSrTiO3 (xe2x80x9cBSTxe2x80x9d) and piezoelectric lead zirconate titanate (xe2x80x9cPZTxe2x80x9d). Preferably, the dielectric layer comprises a material with a high dielectric constant (e.g., at least about 10) such as BST, PZT, or Ta2O5. In one specific embodiment, the dielectric layer is Ta2O5 and is between about 20 xc3x85 and about 200 xc3x85 thick depending on the capacitor plate area.
In one particular embodiment, the pass transistor is formed on a layer of epitaxial silicon. In a more specific embodiment, a doped layer in epitaxial silicon isolates the pass transistor from the second capacitor plate.
In another aspect, the invention provides a method for forming a capacitor on a support structure of an integrated circuit. The process is characterized by forming an electrically isolating support structure on a semiconductor substrate, providing a first capacitor plate on the vertical sidewalls of the support structure, providing a capacitor dielectric on at least a portion of the first capacitor plate and providing a second capacitor plate on a portion of the capacitor dielectric by forming a second conductive layer on the semiconductor substrate in regions outside of the support structure.
In one embodiment the support structure is between about 0.1 micrometer and about 10 micrometers high. In another particular embodiment, the support structure is between about 0.2 micrometers and about 1 micrometer high. In yet another embodiment the support structure is formed by blanket deposition of oxide or spinning on a glass.
The first capacitor plate may be formed by a process where the support structure is patterned to expose regions of the semiconductor substrate, blanket deposition of a liner layer, blanket deposition of a first conductive layer on the liner layer and anisotropically etching the first conductive layer so that it is retained on the vertical sidewalls of the support structure. In one embodiment, the liner layer may be nitride. In another embodiment the first conductive layer may be doped polysilicon. In yet another embodiment, the second conductive layer may be formed by growing doped epitaxial silicon.
The DRAM cell may be completed by a process comprising providing a spacer that electrically isolates the first capacitor plate and the second capacitor plate and forming a pass transistor that is electrically connected to the capacitor. The spacer is provide by a process comprising blanket deposition of nitride and anisotropically etching the nitride so that it is retained on a portion of the first conductive layer, on a portion of the dielectric layer and on a portion of the second conductive layer. In one embodiment a doped layer that isolates said pass transistor from said second conductive layer is formed. In a more specific embodiment, the doped layer includes n-type doped epitaxial silicon. In another embodiment the pass transistor is formed on a layer of epitaxial silicon. In a more specific embodiment the layer of epitaxial silicon is of the p-type.
These and other features and advantages of the present invention will be further described in the following detailed description of the invention with reference to the associated drawings.